1. Field of the Invention
The present invention relates to semiconductor memory devices and more particularly, to a clock control circuit that generates clock signals to control the input operations of an address buffer and control signal buffers of a semiconductor memory device and semiconductor memory device including the same and an input operation method of the semiconductor memory device.
2. Discussion of Related Art
In general, in semiconductor memory devices that operate in synchronization with a clock signal in the same manner as synchronous semiconductor memory devices, an address buffer receives an address signal in synchronization with the clock signal. Furthermore, a control signal buffer also receives an external control signal in synchronization with the clock signal. The input operation of the address buffer and the control signal buffers in the related art will be described below with reference to FIGS. 1 and 2.
FIG. 1 is a block diagram schematically showing a clock control circuit and an address signal buffer and control signal buffers of a semiconductor memory device in the related art. FIG. 2 is a timing diagram of signals related to the operation of the clock control circuit shown in FIG. 1 and buffers for receiving address signals and control signals.
The timing diagram of FIG. 2 is related to the operation of the buffers that receive an address signal and control signals in data write and read operations of the semiconductor memory device.
Referring first to FIG. 1, output terminals of a clock buffer 10 and an address valid signal (/ADV) buffer 20 are connected to input terminals of a clock repeater 30, respectively. The clock repeater 30 includes a clock generator 31 and a control logic circuit 32.
The clock generator 31 includes a pulse signal generator 33 and a delay circuit 34. Furthermore, the delay circuit 34 includes inverters 35, 36 that are connected in series. The control logic circuit 32 includes inverters 37, 38 that are connected in series.
The clock buffer 10 receives an external clock signal (EXCLK) and outputs an input clock signal (CLK). The /ADV the buffer 20 receives an address valid signal (/ADV) and outputs an input address valid signal (ADV0) and an internal address valid signal (KADV), in response to an enable signal (EN) and a control clock signal (CTDB_AC). The internal address valid signal (KADV) is synchronized to the control clock signal (CTDB_AC).
The clock repeater 30 outputs the control clock signal (CTDB_AC) according to the input clock signal (CLK), delays the input address valid signal (ADV0) and outputs a control signal (ADV0)_A).
The address buffer 40 receives an external address signal (ADDR) and outputs an internal address signal (Ai), in response to the control clock signal (CTDB_AC). Furthermore, the address buffer 40 outputs an address transition detection signal (ATD) in response to the control signal (ADV0)_A) and the external address signal (ADDR).
Meanwhile, a plurality of control signal buffers 50A1 to 50AK) (K is an integer) receives external control signals (EXCTL1 to EXCTLK) (K is an integer) and outputs internal control signals (CTL1 to CTLK) (K is an integer), respectively, in response to the control clock signal (CTDB_AC).
As shown in FIG. 2, the clock repeater 30 consecutively outputs the control clock signal (CTDB_AC) whenever the input clock signal (CLK) is received (i.e., whenever the input clock signal (CLK) is toggled). Therefore, even in a period where the valid external address signal (ADDR) is not received, the address buffer 40 consecutively operates in response to the control clock signal (CTDB_AC).
On the other hand, some of the external control signals (EXCTL1 to EXCTLK) are input to the semiconductor memory device only in a specific period similar to the external address signal (ADDR). In this case, control signal buffers (some of 50A1 to 50AK) that receive some of the external control signals (EXCTL1 to EXCTLK), respectively, consecutively operate in response to the control clock signal (CTDB_AC) even in a period where some of the external control signals (some of EXCTL1 to EXCTLK) are not input.
If the clock repeater 30, the address buffer 40 and the control signal buffers (some of 50A1 to 50AK) consecutively operate, an amount of current that is unnecessarily consumed is increased. This will be described in more detail. Each of the inverters 35 to 38 of the clock repeater 30 includes a plurality of transistors (not shown). The transistors include a relatively high current driving ability
The reason why the transistors have a relatively high current driving ability is to supply the control clock signal (CTDB_AC) to the address buffer 30 and control signal buffers (some of 50A1 to 50AK) having a relatively high resistance component. Since the transistors have a relatively high current driving ability as described above, a relatively great amount of current is consumed when the transistors are driven.
Furthermore, power consumption is increased because the address buffer 30 and the control signal buffers (some of 50A1 to 50AK) consecutively operate whenever the control clock signal (CTDB_AC) is toggled.
The clock repeater 30 of the related art is problematic in that an amount of current that is unnecessarily consumed is increased since it consecutively toggles the control clock signal (CTDB_AC) regardless of the address signal or the external control signal as described above.
The problem becomes more profound when semiconductor memory devices including the clock repeater 30 are applied to mobile products. That is, mobile products must operate for a long period of time at low power. Therefore, to reduce power consumption, power consumption of semiconductor chips included in mobile products must be reduced. However, a problem arises because mobile products cannot operate for a long period of time because power consumption of semiconductor memory devices is increased due to the consecutive operation of the clock repeater 30.